1. Field of the Invention
The present invention relates to a method of obtaining self insulated metallizations on a semiconductor component, such as a transistor or an integrated circuit, this method allowing two metallizations to be obtained separated by a distance, measured on the surface of the semiconductor wafer, less than the definition of the masks, that is to say less than the smallest dimension of the masks. The method of the invention applies to the formation of transistors, integrated circuits, loads for transistors, as well as to the crossing of conducting tracks: in fact, the metallizations obtained by this method are self insulated, that is to say covered with an insulating layer. The invention also relates to the semiconductor components produced by this method.
2. Description of the Prior Art
The development of high speed electronics, that is to say that which is formed for example on a III-V material such as GaAs or other comparable materials comes up against two types of difficulties.
The first difficulty is related to the limitation of the definition of the mask. Although optical masking, that is to say obtained by a photon beam, is in many cases superseded by electronic or X ray masking by which lines separated by less than a micron can be formed, it would be desirable to further improve this definition, which would allow higher speed transistors to be obtained, the source/drain distance in the field effect transistors being reduced, and so the transit time of the charge carriers reduced. Such an improvement would be advantageous to the extent that it allows an industrial application resulting in normal manufacturing yields for this type of activity, and to the extent that the breakdown voltages between two metallizations under operating voltage are avoided.
The second difficulty is specific to transistors. In ultra high speed integrated logic circuits, it is very important to reduce the parasite access resistances of the field effect transistors, namely the resistances between source and gate and between gate and drain. Numerous solutions have been proposed. The most usual are: transistors with hollowed out channel and transistors obtained by self aligned implantation. These solutions have given very good results but with very mediocre manufacturing yields because of the difficulties of controlling the threshold voltages in the hollowing out of the channel or in the annealing of the implantations.
On the other hand, the so called planar technology, that is to say that in which the surface of a semiconductor component is flat, has the very great advantage of controlling this threshold voltage well.
With the simplicity of the planar method, the manufacturing yield may be very high. But the weak point of this technology is having parasite access resistances a little higher than in the other methods described.
The invention provides then a new self insulating method which reduces these parasite resistances without losing the advantage of having well controlled threshold voltages. In other words, the invention provides a method for forming at least two metallizations, which are self insulated, and wherein the distance separating them is smaller than that obtained by the methods known up to now.